The present invention relates to a virtual machine system having an address translation look-aside buffer (referred to as TLB).
In the virtual machine system of IBM 370 XA architecture, operation of a virtual machine (hereinafter simply referred to as VM in abbreviation) is started only after a virtual machine start interpretative execution instruction (hereinafter referred to as SIE instruction) has been executed with a host control program. FIG. 1 of the accompanying drawings shows an instruction format for the SIE instruction. As will be seen, the SIE instruction designates as operands the state descripter (hereinafter referred to as SD) which are located and identified by fields B2 and D2, respectively. Upon execution of the SIE instruction, an instruction unit of a central processing unit (hereinafter referred to as CPU) reads out the respective fields of SD from a main storage (hereinafter referred to as MS) and places the SD fields in hardware resource of the CPU to thereby permit the latter to operate as a guest VM. As the hardware resource in which the SD fields can be placed, there may be mentioned a guest mode latch, a program status word (PSW) register, a control register (CR), a general register (GR), a prefix register, an MS extent register and the like. On the other hand, the states of the host is reserved in the CPU. Thus, the SD describes the architecture of the guest VM as viewed from the side of the guest instruction.
The guest VM started in response to the SIE instruction continues to emulate a guest program until interruption or interception takes place. With the term "interruption", it is intended to mean interruptions such as, for example, input/output interruption and external interruption which require processing by the host. The interception may occur at a time point when an instruction requiring processing by the host has to be executed. Whether the interception is to be issued or not for some of privileged instructions can be designated by an interception mask field contained in the SD.
Upon occurrence of the interruption or interception, operation of the guest VM comes to an end, whereupon the CPU is set to the host mode to be restored to a state ready for executing a SIE instruction.
One of the important technological problems in the virtual machine system resides in how to define "main storage" of the guest. In the guest VM started with the SIE instruction, two modes, i.e. pageable storage mode and preferred storage mode are made use of. FIG. 2 of the accompanying drawings illustrates an address translation mechanism in the pageable storage mode. A guest virtual address (GV in abbreviation) is translated to a guest absolute address (referred to as GA) through guest address translation. It is checked for confirmation that the above mentioned GA resides within the MS extent designated by the SD. Subsequently, GA is added with the MS origin (termed MSO in abbreviation) to determine a host virtual address (HV), which is then translated to a host absolute address (HA) through host address translation. In the case of the preferred storage mode, the guest absolute address or GA is regarded to be the host absolute address (HA) without undergoing any address translation. In either mode, a pair of GV and HA are registered as the entries of the address translation look-aside buffer or TLB. Accordingly, by searching the TLB with GV (i.e. guest virtual address), the host absolute address or HA can be determined.
Concerning the TLB structure in the virtual machine system of the architecture described above, a proposal is disclosed in U.S. Pat. No. 4,456,954. According to this known proposal, each entry of the TLB is provided with a guest field of one bit which bit is set to "0" when host address translation information is registered while it is set to "1" when the address translation information for the guest VM is registered. With this arrangement, it is possible to discriminate the host entry and the guest entry from each other, to thereby allow the host address translation information together with the address translation information of one virtual machine or VM to be simultaneously held in the translation look-aside buffer or TLB. However, in view of the fact that the number of the guest VM which can be held in the TLB is limited to one, it is necessary to invalidate all the guest entries for the guest VM, when the execution of the guest VM is to be ended upon occurrence of the interruption or interception, by way of example. As a consequence, when the guest VM under consideration is to be started again by the SIE instruction, the address translation has to be performed even for making access to the entries registered at the time the preceding execution by the guest VM was ended, involving excessive overhead, which is of course undesirable from the standpoint of the instruction processing performance. In order to solve the problem mentioned above, it is necessary to implement the TLB in such a structure that the host address translation information together with the address translation information for a plurality of guest VMs can be simultaneously held and to provide means to discriminatably identify the guest VM.
As a hitherto known system including the means for discriminating or identifying the guest VM there can be mentioned the one disclosed in Japanese Patent Kokoku No. (JP-B-57-23347) (JP-A-55-113182). According to the teaching in this system, a VM-ID (a start address or end address of a location allocated on MS by an MS monitor) is utilized as the guest VM identifying information, wherein a field is provided for storing VM-ID in the address translation look-aside buffer (TLB) in combination with a register for placing therein the VM-ID. Upon retrieval of the address translation look-aside buffer or TLB, the VM-ID is previously set in the abovementioned register, wherein the VM-ID read out from the TLB is compared with the VM-ID placed in the register to thereby allow the translation of GV (guest virtual address) to HA (host absolute address) only when the comparison results in coincidence. According to this prior art technique, the content of the address translation look-aside buffer need not be cleared but can be utilized as it is even when the control is transferred from a certain guest VM to another guest VM.
However, the VM-ID is managed by the VM monitor of software nature, and it is impossible to identify what is assigned as the VM-ID when viewed from the side of hardware. Consequently, when VM-ID is to be placed in the register, it is necessary to detect by means of software what is assigned as the VM-ID, load the register with the VM-ID detected by software and start execution of the guest VM by software.